1. Field of the Invention
The present invention generally relates to a local input/output line precharge circuit of a semiconductor memory device, and more specifically, to a technology of reducing current consumption by omitting a local input/output line precharge operation at a continuous write mode.
2. Description of the Related Art
Generally, a semiconductor memory device performs a precharge operation on a pair of local input/output lines at a read and write modes. That is, the pair of local input/output lines transmit a data signal between a pair of global input/output lines and an internal circuit. Here, the semiconductor memory device precharge the pair of local input/output lines at every read or write command, and then the accurate data signal can be transmitted.
FIG. 1 is a diagram illustrating the local input/output line precharge circuit of a conventional semiconductor memory device.
The conventional local input/output line precharge circuit comprises a precharge control unit 10, an equalization unit 20 and a data output unit 30.
The precharge control unit 10 which comprises inverters IV1 and IV2 drives a precharge signal LIO_RST to output a precharge control signal IOEQ.
The equalization unit 20 equalizes the pair of local input/output lines LIO and LIOb in response to the precharge control signal IOEQ. Here, the equalization unit 20 comprises NMOS transistors NM1˜NM3 which are controlled by the precharge control signal IOEQ. The NMOS transistors NM1 and NM2 have drains to receive a precharge voltage VBLP, and sources connected to the pair of local input/output lines LIO and LIOb, respectively. The NMOS transistor NM3, which has a drain and a source connected to the sources of the NMOS transistors NM1 and NM2, equalizes the pair of local input/output lines LIO and LIOb.
The data output unit 30 outputs data signals of the pair of global input/output lines GIO and GIOb to the pair of local input/output lines LIO and LIOb in the write mode. Here, the data output unit 30 comprises a write driver control unit 31, a global input/output line bar output unit 32, a global input/output line output unit 33, a pull-up driver 34, a pull-down driver 35, latch units 36 and 37, a local input/output line driving unit 38, and a local input/output line bar driving unit 39.
The write driver control unit 31 comprises a NAND gate ND1 and an inerter IV3.
The NAND gate ND1 performs a NAND operation on a write driver enable signal BWEN and a write driver stop signal BAYBD. The inverter IV3 inverts an output signal from the NAND gate ND1.
The global input/output line bar output unit 32 outputs a data signal of the global input/output line GIO in response to a data masking bar signal WDMb and an output signal BWEN1 from the NAND gate ND1. Here, the global input/output line bar output unit 32 comprises a global input/output line bar driving unit 41 and a latch unit 42.
The global input/output line bar driving unit 41 comprises PMOS transistors PM1 and PM2 that have drains to receive a power voltage VDD level in response to the data masking bar signal WDMb and a global input/output line bar signal GIOb respectively, and NMOS transistors NM4˜NM6 that are controlled by the global input/output line bar signal GIOb, the data masking bar signal WDMb and an output signal BWEN1 from the NAND gate ND1 respectively. The PMOS transistor PM1 and the NMOS transistors NM4˜NM6 are connected serially between a power voltage terminal and a ground voltage terminal. The PMOS transistor PM2 is connected between the power voltage terminal and the drain of the PMOS transistor PM1.
The latch unit 42, which comprises inverter IV4 and IV5 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line bar driving unit 41 at a predetermined level.
The global input/output line output unit 33 outputs the data signal BWEN1 of the global input/output line GIO in response to the data masking bar signal WDMb and the output signal from the NAND gate ND1. Here, the global input/output line output unit 33 comprises PMOS transistors PM3 and PM4 that have drains to receive the power voltage VDD level in response to the data masking bar signal WDMb and the global input/output line signal GIO respectively, and NMOS transistors NM7˜NM9 that are controlled by the global input/output line signal GIO, the data masking bar signal WDMb and the output signal BWEN1 from the NAND gate ND1 respectively. The PMOS transistor PM3 and the NMOS transistors NM7˜NM9 are connected serially between the power voltage terminal and the ground voltage terminal, and the PMOS transistor PM4 is connected between the power voltage terminal and the drain of the PMOS transistor PM3.
The latch unit 44, which comprises inverters IV6 and IV7 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line driving unit 43 at a predetermined level.
The pull-up driver 34 comprises a PMOS transistor PM5, NMOS transistors NM10 and NM11 which are connected serially between the power voltage VDD terminal and the ground voltage terminal. Here, the PMOS transistor PM5 applies a power voltage level to a node N1 in response to an output signal from the inverter IV1, and the NMOS transistors NM10 and NM11 are connected serially between the node N1 and the ground voltage terminal. The NMOS transistor NM10 is controlled by an output signal BWEN2 from the inverter IV3, and the NMOS transistor NM11 is controlled by an output signal from the global input/output line bar output unit 32, thereby applying a ground voltage level signal to the node N1.
The pull-down driver 35 comprises a PMOS transistor PM6 and NMOS transistors NM12 and NM13 which are connected serially between the power voltage VDD terminal and the ground voltage terminal.
The PMOS transistor PM6 applies the power voltage level to a node N2 in response to the output signal from the inverter IV1, and the NMOS transistors NM12 and NM13 are connected serially between the node N2 and the ground voltage terminal. The NMOS transistor NM12 is controlled by the output signal BWEN2 from the inverter IV3, and the NMOS transistor NM13 is controlled by an output signal from the global input/output line output unit 33, thereby applying the ground voltage level signal to the node N2.
The latch unit 36 which comprises inverters IV8 and IV9 maintains a potential of the node N1 at a predetermined level, and the latch unit 37 which comprises inverters IV10 and IV11 maintains a potential of the node N2 at a predetermined level.
The local input/output line driving unit 38 comprises an inverter IV12, a PMOS transistor PM7 and a NMOS transistor NM14. Here, the inverter IV12 inverts an output signal from the latch unit 37, the PMOS transistor PM7 applies a core voltage VCORE level to a node N3 in response to an output signal from the inverter IV12, and the NMOS transistor N14 applies the ground voltage level to the node N3 in response to an output signal from the latch unit 36.
The local input/output line bar driving unit 39 comprises an inverter IV13, a PMOS transistor PM8 and a NMOS transistor NM15. Here, the inverter IV13 inverts an output signal from the latch unit 36, the PMOS transistor PM8 applies the core voltage VCORE level to a node N4 in response to an output signal from the inverter IV13, and the NMOS transistor NM15 applies the ground voltage level to the node N4 in response to an output signal from the latch unit 37. The above-described conventional local input/output lines precharge circuit precharges a pair of local input/output lines at a predetermined level in the write and read modes, and then operates a write driver or input/output sense amplifier to transmit the data signal
However, although the write driver changes the levels of the pair of local input/output lines even when the pair of local input/output lines are not precharged, as shown in FIG. 2, the write driver precharges the pair of local input/output lines at a continuous write mode, and loads data to precharge the pair of local input/output lines, repeatedly. As a result, the conventional circuit performs an unnecessary precharge operation at the continuous write mode, which results in increase of current consumption.